Circuit Design , Transistor Sizing and Wire Layout of FPGA Interconnect

This paper examines the electrical design of FPGA interconnect circuitry. We explore the circuit design of pass transistor and tri-state buffer routing switches, determine which transistor sizing, metal width and metal spacing are best for FPGA interconnect, and show that FPGA interconnect should be electrically heterogeneous-some (~20%) of the routing tracks should be designed for maximum speed while the remainder should be more area-efficient. 1. Introduction While considerable research has investigated the optimization of FPGA routing architecture (the lengths of the routing wire segments and the pattern of routing switches used to interconnect them [1]), relatively little has been published concerning the electrical optimization of FPGA interconnect. Little is known about the best circuit design and transistor sizing for the routing switches themselves. Similarly, there has been no published work examining the layout of FPGA routing wire segments, despite the fact that using the proper metal width and spacing in deep-submicron processes is crucial to obtain the best circuit speed [2]. The programmable routing accounts for most of the area and most of the delay in FPGAs [1], so fast and area-efficient circuitry is essential. In this paper we explore four related issues: the circuit design of pass transistor and tri-state buffer routing switches, the best transistor sizes to use in both types of switch, how routing wires should be laid out (what metal width and spacing is best?), and electrically-heterogeneous FPGAs, in which some routing wires are tuned for density and some for speed. Considering the importance of the electrical design of its routing to an FPGA's speed and density, there is relatively little published prior work. In [3, 4], Chow et al discussed the implementation of an SRAM-based FPGA in a 1.2 µm CMOS process, and highlighted many circuit design issues. In [5], Khellah, Brown and Vranesic performed some transistor-sizing experiments on pass transistor routing switches in a 0.8 µm process. In [6], Dobbelaere, Horowitz and El Gamal proposed an innovative regenerative feedback circuit element to speed FPGA routing. This paper is organized as follows. The next section describes the class of FPGAs we are investigating, and discusses two important circuit issues in the design of FPGA routing switches. In Section 3 we determine which transistor sizes lead to FPGA interconnect with the best area-delay product , and in Section 4 we investigate the effect of different routing wire metal widths and spacings. Section 5 examines " electrically-heterogeneous …